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MTB2P50E
Preferred Device
Power MOSFET 2 Amps, 500 Volts
P-Channel D2PAK
This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltage-blocking capability without degrading performance over time. In addition, this Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The energy efficient design also offers a drain-to-source diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients.
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2 AMPERES, 500 VOLTS RDS(on) = 6 W
P-Channel D
* Robust High Voltage Termination * Avalanche Energy Specified * Source-to-Drain Diode Recovery Time Comparable to a Discrete * * * * *
Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Short Heatsink Tab Manufactured -- Not Sheared Specially Designed Leadframe for Maximum Power Dissipation Pb-Free Package is Available
Rating Drain-Source Voltage Drain-Gate Voltage (RGS = 1.0 MW) Gate-Source Voltage - Continuous Non-Repetitive (tp 10 ms) Drain Current - Continuous Drain Current - Continuous @ 100C Drain Current - Single Pulse (tp 10 ms) Total Power Dissipation Derate above 25C Total Power Dissipation @ TA = 25C (Note 1) Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 100 Vdc, VGS = 10 Vdc, IL = 4.0 Apk, L = 10 mH, RG = 25 W) Thermal Resistance - Junction-to-Case - Junction-to-Ambient - Junction-to-Ambient (Note 1) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 sec Symbol VDSS VDGR VGS VGSM ID ID IDM PD Value 500 500 20 40 2.0 1.6 6.0 75 0.6 2.5 -55 to 150 80 Unit Vdc Vdc Vdc Vpk Adc Apk W W/C C mJ
G S
D2PAK CASE 418B STYLE 2 1
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
MARKING DIAGRAM & PIN ASSIGNMENT
4 Drain T P50EG AYWW 1 Gate 2
2 Drain
3 Source
TJ, Tstg EAS
T2P50E A Y WW G
= Device Code = Assembly Location = Year = Work Week = Pb-Free Package
ORDERING INFORMATION
C/W RqJC RqJA RqJA TL 1.67 62.5 50 260 C Device MTB2P50ET4 MTB2P50ET4G Package D2PAK D2PAK (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Preferred devices are recommended choices for future use and best overall value.
Shipping 800/Tape & Reel 800/Tape & Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. When surface mounted to an FR4 board using the minimum recommended pad size.
(c) Semiconductor Components Industries, LLC, 2006
1
June, 2006 - Rev. 4
Publication Order Number: MTB2P50E/D
MTB2P50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS Drain-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 500 Vdc, VGS = 0 Vdc) (VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 2) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) Static Drain-Source On-Resistance (VGS = 10 Vdc, ID = 1.0 Adc) Drain-Source On-Voltage (VGS = 10 Vdc) (ID = 2.0 Adc) (ID = 1.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 3) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (See Figure 8) (VDS = 400 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 250 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 9.1 W) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 2) (IS = 2.0 Adc, VGS = 0 Vdc) (IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125C) VSD - - trr (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 2. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 3. Switching characteristics are independent of operating junction temperature. LD - LS - 4.5 7.5 - - nH nH ta tb QRR - - - - 2.3 1.85 223 161 62 1.92 3.5 - - - - - mC ns Vdc - - - - - - - - 12 14 21 19 19 3.7 7.9 9.9 24 28 42 38 27 - - - nC ns (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - 845 100 26 1183 140 52 pF VGS(th) 2.0 - RDS(on) VDS(on) - - gFS 1.5 9.5 - 2.9 14.4 12.6 - mhos - 3.0 4.0 4.5 4.0 - 6.0 Vdc mV/C W Vdc V(BR)DSS 500 - IDSS - - IGSS - - - - 10 100 100 nAdc - 564 - - Vdc mV/C mAdc Symbol Min Typ Max Unit
Reverse Recovery Time (See Figure 14)
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MTB2P50E
TYPICAL ELECTRICAL CHARACTERISTICS
4 I D , DRAIN CURRENT (AMPS) I D , DRAIN CURRENT (AMPS) 3.5 3 2.5 2 1.5 1 0.5 4V 0 0 4 12 16 8 20 24 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 28 0 2 2.5 3 4 5 6 3.5 4.5 5.5 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 6.5 7 5V 6V TJ = 25C VGS = 10 V 7V 8V 4 3.5 3 2.5 2 1.5 1 0.5 TJ = - 55C
VDS 10 V 100C 25C
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
10 8 6
VGS = 10 V TJ = 100C
6 5.75 5.5 5.25 5 4.75 15 V 4.5 4.25 4 0 0.5 1 2 3 1.5 2.5 ID, DRAIN CURRENT (AMPS) 3.5 4 VGS = 10 V TJ = 25C
25C 4 - 55C 2
0
0
0.5
1
2 2.5 1.5 3 ID, DRAIN CURRENT (AMPS)
3.5
4
Figure 3. On-Resistance versus Drain Current and Temperature
Figure 4. On-Resistance versus Drain Current and Gate Voltage
RDS(on), DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2 VGS = 10 V ID = 1 A 1.5
1000 VGS = 0 V TJ = 125C I DSS , LEAKAGE (nA) 100 100C
1
10 25C
0.5 - 50
- 25
0
25
50
75
100
125
150
1
0
50
100
150
200
250
300
350
400
450
500
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-To-Source Leakage Current versus Voltage
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MTB2P50E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP)
1800 1600 1400 C, CAPACITANCE (pF) 1200 1000 800 600 400 200 0 10 5 VGS 0 VDS Crss 5 Coss 10 15 20 25 1 10 100 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 1000 Crss Ciss VDS = 0 V Ciss C, CAPACITANCE (pF) 100 Coss 10 Crss VGS = 0 V TJ = 25C
The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.
1000
VGS = 0 V TJ = 25C
Ciss
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
Figure 7b. High Voltage Capacitance Variation
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MTB2P50E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 12 QT VGS 8 Q1 6 4 2 Q3 0 0 2 4 6 8 10 12 14 VDS 16 18 QT, TOTAL CHARGE (nC) Q2 ID = 2 A TJ = 25C 150 100 50 0 20 200 10 300 250 1000 VDD = 250 V ID = 2 A VGS = 10 V TJ = 25C t, TIME (ns) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
100 tf td(off)
tr 10 1 10
td(on) 100
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate-To-Source and Drain-To-Source Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation versus Gate Resistance
DRAIN-TO-SOURCE DIODE CHARACTERISTICS
2 VGS = 0 V TJ = 25C
IS , SOURCE CURRENT (AMPS)
1.6
1.2
0.8
0.4
0 0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance-General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A Power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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MTB2P50E
SAFE OPERATING AREA
10 I D , DRAIN CURRENT (AMPS) 80 10 ms E , SINGLE PULSE DRAIN-TO-SOURCE AS AVALANCHE ENERGY (mJ) VGS = 20 V SINGLE PULSE TC = 25C 100 ms 1 ms 0.1 10 ms RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 0.1 1 10 100 1000 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) dc
ID = 2 A
60
1
40
20
0.01
0
25
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 11. Maximum Rated Forward Biased Safe Operating Area
Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature
1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE D = 0.5 0.2 0.1 0.1 0.01 SINGLE PULSE t2 DUTY CYCLE, D = t1/t2 1.0E-03 1.0E-02 t, TIME (s) 1.0E-01 t1 0.05 0.02 P(pk) RqJC(t) = r(t) RqJC D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RqJC(t)
0.01 1.0E-05
1.0E-04
1.0E+00
1.0E+01
Figure 13. Thermal Response
3 PD, POWER DISSIPATION (WATTS) 2.5 2.0 1.5 1 0.5 0 25
RqJA = 50C/W Board material = 0.065 mil FR-4 Mounted on the minimum recommended footprint Collector/Drain Pad Size 450 mils x 350 mils
di/dt IS trr ta tb TIME tp IS 0.25 IS
50
75
100
125
150
TA, AMBIENT TEMPERATURE (C)
Figure 14. Diode Reverse Recovery Waveform
Figure 15. D2PAK Power Derating Curve
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MTB2P50E
PACKAGE DIMENSIONS
D2PAK 3 CASE 418B-04 ISSUE J
C E -B-
4 DIM A B C D E F G H J K L M N P R S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. 418B-01 THRU 418B-03 OBSOLETE, NEW STANDARD 418B-04. INCHES MIN MAX 0.340 0.380 0.380 0.405 0.160 0.190 0.020 0.035 0.045 0.055 0.310 0.350 0.100 BSC 0.080 0.110 0.018 0.025 0.090 0.110 0.052 0.072 0.280 0.320 0.197 REF 0.079 REF 0.039 REF 0.575 0.625 0.045 0.055 MILLIMETERS MIN MAX 8.64 9.65 9.65 10.29 4.06 4.83 0.51 0.89 1.14 1.40 7.87 8.89 2.54 BSC 2.03 2.79 0.46 0.64 2.29 2.79 1.32 1.83 7.11 8.13 5.00 REF 2.00 REF 0.99 REF 14.60 15.88 1.14 1.40
V W
A
1 2 3
S
-T-
SEATING PLANE
K G D 3 PL 0.13 (0.005) H
M
W J
TB
M
VARIABLE CONFIGURATION ZONE L M
R
N U L
P L M
STYLE 2: PIN 1. GATE 2. DRAIN 3. SOURCE 4. DRAIN
M
F VIEW W-W 1
F VIEW W-W 2
F VIEW W-W 3
SOLDERING FOOTPRINT*
8.38 0.33
10.66 0.42
1.016 0.04
5.08 0.20
3.05 0.12 17.02 0.67
SCALE 3:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MTB2P50E
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MTB2P50E/D

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